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To achieve this, Sony AI is working across six Flagship Projects that are aimed at the evolution and application of AI technology in the areas of AI for Creators, Gaming and Interactive Agents, Ethics, Scientific Discovery, Imaging and Sensing, and Robotics and Sensing. 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Its purpose is to operate for educational, scientific and technical purposes for the benefit of the international electronics design and design automation community. The Association, in the field of design and design automation of electronic circuits and systems, promotes a series of high quality technical international conferences and workshops across Europe and cooperates actively to maintain harmonious relationships with other national and international technical societies and groups promoting the purpose of the Association. EDAA is the main sponsor of DATE, the premier Design, Automation and Test Conference and Exhibition in Europe.\u003C/p>","2025-09-22T13:12:43.375Z","2025-09-22T13:12:45.344Z","2025-09-22T13:12:45.337Z","167",{"id":444,"name":1342,"alternativeText":13,"caption":13,"width":1343,"height":1344,"formats":1345,"hash":1364,"ext":954,"mime":957,"size":1365,"url":1366,"previewUrl":13,"provider":54,"provider_metadata":13,"createdAt":1367,"updatedAt":1367},"EDAA.jpg",992,742,{"small":1346,"medium":1352,"thumbnail":1358},{"ext":954,"url":1347,"hash":1348,"mime":957,"name":1349,"path":13,"size":1350,"width":35,"height":1351},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad25/small_EDAA_81b5e0d994.jpg","small_EDAA_81b5e0d994","small_EDAA.jpg",18.3,374,{"ext":954,"url":1353,"hash":1354,"mime":957,"name":1355,"path":13,"size":1356,"width":42,"height":1357},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad25/medium_EDAA_81b5e0d994.jpg","medium_EDAA_81b5e0d994","medium_EDAA.jpg",30.46,561,{"ext":954,"url":1359,"hash":1360,"mime":957,"name":1361,"path":13,"size":1362,"width":1363,"height":50},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad25/thumbnail_EDAA_81b5e0d994.jpg","thumbnail_EDAA_81b5e0d994","thumbnail_EDAA.jpg",6.19,209,"EDAA_81b5e0d994",42.3,"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad25/EDAA_81b5e0d994.jpg","2025-09-22T13:12:27.165Z",{"id":1154,"variation":58,"button":1369},[1370],{"id":1371,"label":116,"size":62,"color":63,"style":13,"icon":117,"iconPosition":65,"url":1372,"newWindow":8,"downloadable":13,"shape":13},75,"https://www.edaa.com","-121",{"id":181,"name":1045,"description":76,"createdAt":1375,"updatedAt":1376,"publishedAt":1377,"url_path_id":1378,"logo":1379,"website":1382,"url_path":1386},"2025-10-14T15:00:30.165Z","2025-10-14T15:00:49.087Z","2025-10-14T15:00:49.081Z","177",{"id":849,"name":1052,"alternativeText":13,"caption":13,"width":35,"height":1053,"formats":1380,"hash":1061,"ext":22,"mime":25,"size":1062,"url":1063,"previewUrl":13,"provider":54,"provider_metadata":13,"createdAt":1064,"updatedAt":1064},{"thumbnail":1381},{"ext":22,"url":1056,"hash":1057,"mime":25,"name":1058,"path":13,"size":1059,"width":105,"height":1060},{"id":1079,"variation":58,"button":1383},[1384],{"id":1385,"label":116,"size":62,"color":63,"style":13,"icon":117,"iconPosition":65,"url":1069,"newWindow":8,"downloadable":13,"shape":13},76,"-129",{"id":397,"name":1243,"description":1388,"createdAt":1389,"updatedAt":1390,"publishedAt":1391,"url_path_id":1392,"logo":1393,"website":1399,"url_path":1403},"\u003Cp>Current Listing: https://ai.sony/joinus/job-roles/Research_Scientist%E2%80%93AI_for_Digital_Circuit_Design/\u003C/p>","2025-10-14T15:01:04.378Z","2025-10-27T14:05:40.570Z","2025-10-14T15:01:15.683Z","178",{"id":384,"name":1250,"alternativeText":13,"caption":13,"width":1251,"height":1252,"formats":1394,"hash":1277,"ext":22,"mime":25,"size":1278,"url":1279,"previewUrl":13,"provider":54,"provider_metadata":13,"createdAt":1280,"updatedAt":1280},{"large":1395,"small":1396,"medium":1397,"thumbnail":1398},{"ext":22,"url":1255,"hash":1256,"mime":25,"name":1257,"path":13,"size":1258,"width":28,"height":1259},{"ext":22,"url":1261,"hash":1262,"mime":25,"name":1263,"path":13,"size":1264,"width":35,"height":1265},{"ext":22,"url":1267,"hash":1268,"mime":25,"name":1269,"path":13,"size":1270,"width":42,"height":1271},{"ext":22,"url":1273,"hash":1274,"mime":25,"name":1275,"path":13,"size":1276,"width":105,"height":849},{"id":1239,"variation":58,"button":1400},[1401],{"id":1402,"label":116,"size":62,"color":63,"style":13,"icon":117,"iconPosition":65,"url":1285,"newWindow":8,"downloadable":13,"shape":13},77,"-130",{"id":418,"name":1405,"description":76,"createdAt":1406,"updatedAt":1407,"publishedAt":1408,"url_path_id":1409,"logo":1410,"website":1441,"url_path":1445},"NVIDIA","2025-10-14T15:02:48.706Z","2025-10-14T15:03:03.820Z","2025-10-14T15:02:50.262Z","179",{"id":1265,"name":1411,"alternativeText":13,"caption":13,"width":1412,"height":1413,"formats":1414,"hash":1437,"ext":22,"mime":25,"size":1438,"url":1439,"previewUrl":13,"provider":54,"provider_metadata":13,"createdAt":1440,"updatedAt":1440},"NVIDIA_logo.svg.png",2560,469,{"large":1415,"small":1421,"medium":1426,"thumbnail":1432},{"ext":22,"url":1416,"hash":1417,"mime":25,"name":1418,"path":13,"size":1419,"width":28,"height":1420},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad25/large_NVIDIA_logo_svg_1ae5067cd9.png","large_NVIDIA_logo_svg_1ae5067cd9","large_NVIDIA_logo.svg.png",32.11,183,{"ext":22,"url":1422,"hash":1423,"mime":25,"name":1424,"path":13,"size":1425,"width":35,"height":346},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad25/small_NVIDIA_logo_svg_1ae5067cd9.png","small_NVIDIA_logo_svg_1ae5067cd9","small_NVIDIA_logo.svg.png",14.26,{"ext":22,"url":1427,"hash":1428,"mime":25,"name":1429,"path":13,"size":1430,"width":42,"height":1431},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad25/medium_NVIDIA_logo_svg_1ae5067cd9.png","medium_NVIDIA_logo_svg_1ae5067cd9","medium_NVIDIA_logo.svg.png",21.56,137,{"ext":22,"url":1433,"hash":1434,"mime":25,"name":1435,"path":13,"size":1436,"width":105,"height":452},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad25/thumbnail_NVIDIA_logo_svg_1ae5067cd9.png","thumbnail_NVIDIA_logo_svg_1ae5067cd9","thumbnail_NVIDIA_logo.svg.png",6.37,"NVIDIA_logo_svg_1ae5067cd9",18.15,"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad25/NVIDIA_logo_svg_1ae5067cd9.png","2025-10-14T15:02:18.862Z",{"id":1284,"variation":58,"button":1442},[1443],{"id":1117,"label":116,"size":62,"color":63,"style":13,"icon":117,"iconPosition":65,"url":1444,"newWindow":8,"downloadable":13,"shape":13},"https://www.nvidia.com/en-us/","-131",{"id":288,"name":1447,"description":1448,"createdAt":1449,"updatedAt":1450,"publishedAt":1451,"url_path_id":1452,"logo":1453,"website":1486,"url_path":1490},"IBM","\u003Cp style=\"text-align:justify;\">Our dynamic global team is looking to enlist enthusiastic professionals to join world-class hardware design teams responsible for developing the most challenging and complex systems in the world. We are seeking energetic, highly-motivated individuals willing to go the extra mile with the aim of helping the overall IBM development team. Strong interpersonal skills are needed to coordinate deliverables and requirements from several areas within and outside of the organization.  There are many opportunities to gain and utilize a deep understanding of future issues and provide input towards decisions affecting system development, logical and physical design as well as sophisticated methodology directions.\u003C/p>\u003Cp style=\"text-align:justify;\"> \u003C/p>\u003Cp style=\"text-align:justify;\">Individuals who are chosen to become a part of our world class development teams will be helping advance IBM’s leadership in developing the highest performing computers and changing hardware solutions. Do you want to be an IBMer? \u003Cstrong>Come THINK with us! \u003C/strong>\u003C/p>\u003Cp style=\"margin-left:0px;text-align:justify;\">\u003Cspan style=\"color:black;\">\u003Cstrong>All interested students can apply at:  \u003C/strong>\u003C/span>\u003Ca target=\"_blank\" rel=\"noopener noreferrer\" href=\"https://urldefense.com/v3/__https://www.ibm.com/careers__;!!IKRxdwAv5BmarQ!cDgYJIULzBRjz6bEV4WJ2tneCNE8KCO8PNlhAU55Es7H-s7F8WTBy8mohtRrCxdpP6ND3lX6BRjYuiv13ExN$\">\u003Cspan style=\"color:black;\">\u003Cstrong>https://www.ibm.com/careers\u003C/strong>\u003C/span>\u003C/a>\u003C/p>\u003Cp style=\"margin-left:0px;\">\u003Cspan style=\"color:black;\">Job # 55016:       \u003C/span>\u003Cspan style=\"color:rgb(200,38,19);\">USA \u003C/span>\u003Ca target=\"_blank\" rel=\"noopener noreferrer\" href=\"https://urldefense.com/v3/__https://ibmglobal.avature.net/en_US/careers/JobDetail?jobId=55106__;!!IKRxdwAv5BmarQ!cDgYJIULzBRjz6bEV4WJ2tneCNE8KCO8PNlhAU55Es7H-s7F8WTBy8mohtRrCxdpP6ND3lX6BRjYut81G66h$\">\u003Cspan style=\"color:black;\">Hardware Developer Intern: 2026\u003C/span>\u003C/a>\u003C/p>\u003Cp style=\"margin-left:0px;\">\u003Cspan style=\"color:black;\">Job # 54841:       \u003C/span>\u003Cspan style=\"color:rgb(200,38,19);\">USA \u003C/span>\u003Ca target=\"_blank\" rel=\"noopener noreferrer\" href=\"https://urldefense.com/v3/__https://ibmglobal.avature.net/en_US/careers/JobDetail?jobId=54841__;!!IKRxdwAv5BmarQ!cDgYJIULzBRjz6bEV4WJ2tneCNE8KCO8PNlhAU55Es7H-s7F8WTBy8mohtRrCxdpP6ND3lX6BRjYum4MKv3W$\">\u003Cspan style=\"color:black;\">Entry Level Hardware Developer: 2026  \u003C/span>\u003C/a>\u003C/p>\u003Cp style=\"margin-left:0px;\">\u003Cspan style=\"color:black;\">Job # 57950:       \u003C/span>\u003Cspan style=\"color:rgb(200,38,19);\">USA \u003C/span>\u003Ca target=\"_blank\" rel=\"noopener noreferrer\" href=\"https://urldefense.com/v3/__https://ibmglobal.avature.net/en_US/careers/JobDetail?jobId=57950__;!!IKRxdwAv5BmarQ!cDgYJIULzBRjz6bEV4WJ2tneCNE8KCO8PNlhAU55Es7H-s7F8WTBy8mohtRrCxdpP6ND3lX6BRjYuiwa32YB$\">\u003Cspan style=\"color:black;\">Software Engineer Intern: 2026\u003C/span>\u003C/a>\u003C/p>\u003Cp style=\"margin-left:0px;\">\u003Cspan style=\"color:black;\">Job # 57952:       \u003C/span>\u003Cspan style=\"color:rgb(200,38,19);\">USA \u003C/span>\u003Ca target=\"_blank\" rel=\"noopener noreferrer\" href=\"https://urldefense.com/v3/__https://ibmglobal.avature.net/en_US/careers/JobDetail?jobId=57952__;!!IKRxdwAv5BmarQ!cDgYJIULzBRjz6bEV4WJ2tneCNE8KCO8PNlhAU55Es7H-s7F8WTBy8mohtRrCxdpP6ND3lX6BRjYup28ftX9$\">\u003Cspan style=\"color:black;\">Entry Level Software Engineer: 2026   \u003C/span>\u003C/a>\u003C/p>\u003Cp style=\"margin-left:0px;\">\u003Cspan style=\"color:black;\"> \u003C/span>\u003C/p>\u003Cp style=\"margin-left:0px;\">\u003Cspan style=\"color:black;\">Job # 49799:    \u003C/span>\u003Cspan style=\"color:rgb(200,38,19);\">Germany \u003C/span>\u003Ca target=\"_blank\" rel=\"noopener noreferrer\" href=\"https://urldefense.com/v3/__https://ibmglobal.avature.net/en_US/careers/JobDetail?jobId=49799__;!!IKRxdwAv5BmarQ!cDgYJIULzBRjz6bEV4WJ2tneCNE8KCO8PNlhAU55Es7H-s7F8WTBy8mohtRrCxdpP6ND3lX6BRjYupH2q6oL$\">\u003Cspan style=\"color:black;\">System and Board Design Engineer: 2026\u003C/span>\u003C/a>\u003C/p>\u003Cp style=\"margin-left:0px;\">\u003Cspan style=\"color:black;\">Job # 64045:    \u003C/span>\u003Cspan style=\"color:rgb(200,38,19);\">Germany \u003C/span>\u003Ca target=\"_blank\" rel=\"noopener noreferrer\" href=\"https://urldefense.com/v3/__https://ibmglobal.avature.net/en_US/careers/JobDetail?jobId=64045__;!!IKRxdwAv5BmarQ!cDgYJIULzBRjz6bEV4WJ2tneCNE8KCO8PNlhAU55Es7H-s7F8WTBy8mohtRrCxdpP6ND3lX6BRjYupGbBg3j$\">\u003Cspan style=\"color:black;\">Chip & Hardware Test Technician: 2026\u003C/span>\u003C/a>\u003C/p>\u003Cp style=\"margin-left:0px;\">\u003Cspan style=\"color:black;\">Job # 54047:    \u003C/span>\u003Cspan style=\"color:rgb(200,38,19);\">Germany \u003C/span>\u003Ca target=\"_blank\" rel=\"noopener noreferrer\" href=\"https://urldefense.com/v3/__https://ibmglobal.avature.net/en_US/careers/JobDetail?jobId=54047__;!!IKRxdwAv5BmarQ!cDgYJIULzBRjz6bEV4WJ2tneCNE8KCO8PNlhAU55Es7H-s7F8WTBy8mohtRrCxdpP6ND3lX6BRjYuqt8MU7J$\">\u003Cspan style=\"color:black;\">Linux System Performance Architect: 2026\u003C/span>\u003C/a>\u003C/p>","2025-10-21T13:17:29.423Z","2025-10-25T08:26:00.917Z","2025-10-21T13:17:31.401Z","186",{"id":1454,"name":1455,"alternativeText":13,"caption":13,"width":1456,"height":1457,"formats":1458,"hash":1482,"ext":954,"mime":957,"size":1483,"url":1484,"previewUrl":13,"provider":54,"provider_metadata":13,"createdAt":1485,"updatedAt":1485},136,"IBM_logo_in.jpg",1783,1265,{"large":1459,"small":1465,"medium":1470,"thumbnail":1476},{"ext":954,"url":1460,"hash":1461,"mime":957,"name":1462,"path":13,"size":1463,"width":28,"height":1464},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad25/large_IBM_logo_in_e1412f8354.jpg","large_IBM_logo_in_e1412f8354","large_IBM_logo_in.jpg",32.82,709,{"ext":954,"url":1466,"hash":1467,"mime":957,"name":1468,"path":13,"size":986,"width":35,"height":1469},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad25/small_IBM_logo_in_e1412f8354.jpg","small_IBM_logo_in_e1412f8354","small_IBM_logo_in.jpg",355,{"ext":954,"url":1471,"hash":1472,"mime":957,"name":1473,"path":13,"size":1474,"width":42,"height":1475},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad25/medium_IBM_logo_in_e1412f8354.jpg","medium_IBM_logo_in_e1412f8354","medium_IBM_logo_in.jpg",23.57,532,{"ext":954,"url":1477,"hash":1478,"mime":957,"name":1479,"path":13,"size":1480,"width":1481,"height":50},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad25/thumbnail_IBM_logo_in_e1412f8354.jpg","thumbnail_IBM_logo_in_e1412f8354","thumbnail_IBM_logo_in.jpg",5.62,220,"IBM_logo_in_e1412f8354",56.55,"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad25/IBM_logo_in_e1412f8354.jpg","2025-10-21T13:17:23.428Z",{"id":106,"variation":58,"button":1487},[1488],{"id":1165,"label":116,"size":62,"color":63,"style":13,"icon":117,"iconPosition":65,"url":1489,"newWindow":8,"downloadable":13,"shape":13},"https://www.ibm.com/us-en","-138",{"id":578,"name":1492,"description":1493,"createdAt":1494,"updatedAt":1495,"publishedAt":1496,"url_path_id":1497,"logo":1498,"website":1529,"url_path":1534},"imec","\u003Cul>\u003Cli>Pathfinding Co-Optimization for Technology and Systems (PACTS):\u003Cul>\u003Cli>\u003Ca target=\"_blank\" rel=\"noopener noreferrer\" href=\"https://www.imec-int.com/en/work-at-imec/job-opportunities/physical-design-researcher\">Physical Design Researcher\u003C/a>\u003C/li>\u003Cli>\u003Ca target=\"_blank\" rel=\"noopener noreferrer\" href=\"https://www.imec-int.com/en/work-at-imec/job-opportunities/team-lead-and-test-chip-architect\">ASIC Test Chip Physical Design Architect\u003C/a>\u003C/li>\u003Cli>\u003Ca target=\"_blank\" rel=\"noopener noreferrer\" href=\"https://www.imec-int.com/en/work-at-imec/job-opportunities/power-and-thermal-integrity-researcher\">Power and Thermal Integrity Researcher\u003C/a>\u003C/li>\u003Cli>\u003Ca target=\"_blank\" rel=\"noopener noreferrer\" href=\"https://www.imec-int.com/en/work-at-imec/job-opportunities/dtco-layout-rd-engineer\">DTCO Layout R&D Engineer\u003C/a>\u003C/li>\u003Cli>\u003Ca target=\"_blank\" rel=\"noopener noreferrer\" href=\"https://www.imec-int.com/en/work-at-imec/job-opportunities/digital-systems-researcher-emerging-memory-technologies\">Digital Systems Researcher in Emerging Memory Technologies\u003C/a>\u003C/li>\u003Cli>\u003Ca target=\"_blank\" rel=\"noopener noreferrer\" href=\"https://www.imec-int.com/en/work-at-imec/job-opportunities/researcher-3d-emerging-memories-dramferroigzo-2t0c\">Researcher in 3D Emerging Memories (DRAM/Ferro/IGZO 2T0C)\u003C/a>\u003C/li>\u003Cli>\u003Ca target=\"_blank\" rel=\"noopener noreferrer\" href=\"https://www.imec-int.com/en/work-at-imec/job-opportunities/compact-modelling-engineer\">Compact Modelling Engineer\u003C/a>\u003C/li>\u003C/ul>\u003C/li>\u003Cli>Compute Systems Architectures (CSA):\u003Cul>\u003Cli>\u003Ca target=\"_blank\" rel=\"noopener noreferrer\" href=\"https://www.imec-int.com/en/work-at-imec/job-opportunities/soc-designer-architect\">SoC Designer/ Architect\u003C/a>\u003C/li>\u003Cli>\u003Ca target=\"_blank\" rel=\"noopener noreferrer\" href=\"https://www.imec-int.com/en/work-at-imec/job-opportunities/principal-ai-high-performance-computing-architect\">AI + HPC hardware performance researcher\u003C/a>\u003C/li>\u003C/ul>\u003C/li>\u003C/ul>\u003Cp style=\"margin-left:15px;\">\u003Ca target=\"_blank\" rel=\"noopener noreferrer\" href=\"https://www.imec-int.com/en/work-at-imec/job-opportunities?type=academic&filters%5B0%5D=%2Fjob_employment_type%2Fphd\">Interested in a PhD at imec? Please check out the PhD opportunities here!\u003C/a>\u003C/p>","2025-10-21T13:18:36.674Z","2025-10-21T15:25:14.744Z","2025-10-21T13:18:39.994Z","187",{"id":1431,"name":1499,"alternativeText":13,"caption":13,"width":1412,"height":1500,"formats":1501,"hash":1525,"ext":22,"mime":25,"size":1526,"url":1527,"previewUrl":13,"provider":54,"provider_metadata":13,"createdAt":1528,"updatedAt":1528},"LOGO-IMEC_black.svg.png",1281,{"large":1502,"small":1507,"medium":1513,"thumbnail":1519},{"ext":22,"url":1503,"hash":1504,"mime":25,"name":1505,"path":13,"size":1506,"width":28,"height":35},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad25/large_LOGO_IMEC_black_svg_04c5c3f74a.png","large_LOGO_IMEC_black_svg_04c5c3f74a","large_LOGO-IMEC_black.svg.png",19.55,{"ext":22,"url":1508,"hash":1509,"mime":25,"name":1510,"path":13,"size":1511,"width":35,"height":1512},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad25/small_LOGO_IMEC_black_svg_04c5c3f74a.png","small_LOGO_IMEC_black_svg_04c5c3f74a","small_LOGO-IMEC_black.svg.png",8.83,250,{"ext":22,"url":1514,"hash":1515,"mime":25,"name":1516,"path":13,"size":1517,"width":42,"height":1518},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad25/medium_LOGO_IMEC_black_svg_04c5c3f74a.png","medium_LOGO_IMEC_black_svg_04c5c3f74a","medium_LOGO-IMEC_black.svg.png",13.43,375,{"ext":22,"url":1520,"hash":1521,"mime":25,"name":1522,"path":13,"size":1523,"width":105,"height":1524},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad25/thumbnail_LOGO_IMEC_black_svg_04c5c3f74a.png","thumbnail_LOGO_IMEC_black_svg_04c5c3f74a","thumbnail_LOGO-IMEC_black.svg.png",4.32,123,"LOGO_IMEC_black_svg_04c5c3f74a",12.04,"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad25/LOGO_IMEC_black_svg_04c5c3f74a.png","2025-10-21T13:18:30.374Z",{"id":1530,"variation":58,"button":1531},73,[1532],{"id":1203,"label":116,"size":62,"color":63,"style":13,"icon":117,"iconPosition":65,"url":1533,"newWindow":8,"downloadable":13,"shape":13},"https://www.imec-int.com/en/work-at-imec/job-opportunities?type=career&filters%5B0%5D=%2Fjob_region%2Fbelgium&filters%5B1%5D=%2Fjob_region%2Fcambridge-uk&filters%5B2%5D=%2Fjob_region%2Fgermany&filters%5B3%5D=%2Fjob_employment_type%2Fpermanent-contract","-139",{"id":236,"name":1536,"description":76,"createdAt":1537,"updatedAt":1538,"publishedAt":1539,"url_path_id":1540,"logo":1541,"website":1556,"url_path":1561},"Peking University","2025-10-27T12:31:39.034Z","2025-10-27T12:31:40.885Z","2025-10-27T12:31:40.874Z","196",{"id":1542,"name":1543,"alternativeText":13,"caption":13,"width":1544,"height":1545,"formats":1546,"hash":1552,"ext":954,"mime":957,"size":1553,"url":1554,"previewUrl":13,"provider":54,"provider_metadata":13,"createdAt":1555,"updatedAt":1555},143,"images.jpg",300,168,{"thumbnail":1547},{"ext":954,"url":1548,"hash":1549,"mime":957,"name":1550,"path":13,"size":1551,"width":105,"height":1431},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad25/thumbnail_images_1d87fa6eb4.jpg","thumbnail_images_1d87fa6eb4","thumbnail_images.jpg",6.48,"images_1d87fa6eb4",8.42,"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad25/images_1d87fa6eb4.jpg","2025-10-27T12:31:24.079Z",{"id":1331,"variation":58,"button":1557},[1558],{"id":1559,"label":116,"size":62,"color":63,"style":13,"icon":117,"iconPosition":65,"url":1560,"newWindow":8,"downloadable":13,"shape":13},81,"https://english.pku.edu.cn/","-147",{"id":256,"name":1288,"description":1563,"createdAt":1564,"updatedAt":1565,"publishedAt":1566,"url_path_id":1567,"logo":1568,"website":1574,"url_path":1577},"\u003Cp>Current Listings: \u003C/p>\u003Cul>\u003Cli>\u003Ca target=\"_blank\" rel=\"noopener noreferrer\" href=\"https://confcats-event-sessions.s3.us-east-1.amazonaws.com/iccad25/uploads/EDA-Router.pdf\">EDA-Router\u003C/a>\u003C/li>\u003Cli>\u003Ca target=\"_blank\" rel=\"noopener noreferrer\" href=\"https://confcats-event-sessions.s3.us-east-1.amazonaws.com/iccad25/uploads/EDA-Timing.pdf\">EDA-Timing\u003C/a>\u003C/li>\u003C/ul>","2025-10-27T12:37:12.998Z","2025-10-27T12:41:59.179Z","2025-10-27T12:41:59.171Z","197",{"id":565,"name":1295,"alternativeText":13,"caption":13,"width":1296,"height":1297,"formats":1569,"hash":1323,"ext":954,"mime":957,"size":1324,"url":1325,"previewUrl":13,"provider":54,"provider_metadata":13,"createdAt":1326,"updatedAt":1326},{"large":1570,"small":1571,"medium":1572,"thumbnail":1573},{"ext":954,"url":1300,"hash":1301,"mime":957,"name":1302,"path":13,"size":1303,"width":28,"height":1304},{"ext":954,"url":1306,"hash":1307,"mime":957,"name":1308,"path":13,"size":1309,"width":35,"height":1310},{"ext":954,"url":1312,"hash":1313,"mime":957,"name":1314,"path":13,"size":1315,"width":42,"height":1316},{"ext":954,"url":1318,"hash":1319,"mime":957,"name":1320,"path":13,"size":1321,"width":105,"height":1322},{"id":1371,"variation":58,"button":1575},[1576],{"id":384,"label":116,"size":62,"color":63,"style":13,"icon":117,"iconPosition":65,"url":1332,"newWindow":8,"downloadable":13,"shape":13},"-148",{"id":373,"name":1158,"description":1579,"createdAt":1580,"updatedAt":1581,"publishedAt":1582,"url_path_id":1583,"logo":1584,"website":1589,"url_path":1592},"\u003Col>\u003Cli>\u003Ca target=\"_blank\" rel=\"noopener noreferrer\" href=\"https://urldefense.com/v3/__https://cadence.wd1.myworkdayjobs.com/en-US/External_Careers/job/PhD-Candidate-in-Functional-Safety-for-AI-Accelerators---Contract-Duration-3-Years--f-m-d-_R50111__;!!IKRxdwAv5BmarQ!fQT9-IhPrQEiaF-bRh8kzm7ZUYiupEAP8lk9hFjLH8gH9DutbG6d_Im9CNd-75rBdJnCUB9XMbzvEYM8EA$\">Ph.D. Candidate in Functional Safety for AI Accelerators - Contract Duration 3 Years (f/m/d), Munich - Germany\u003C/a>\u003C/li>\u003Cli>\u003Ca target=\"_blank\" rel=\"noopener noreferrer\" href=\"https://urldefense.com/v3/__https://cadence.wd1.myworkdayjobs.com/en-US/External_Careers/job/Lead-Application-Engineer_R50649-1__;!!IKRxdwAv5BmarQ!fQT9-IhPrQEiaF-bRh8kzm7ZUYiupEAP8lk9hFjLH8gH9DutbG6d_Im9CNd-75rBdJnCUB9XMbyfv2PFvw$\">Lead Application Engineer, Munich - Germany\u003C/a>\u003C/li>\u003Cli>\u003Ca target=\"_blank\" rel=\"noopener noreferrer\" href=\"https://urldefense.com/v3/__https://cadence.wd1.myworkdayjobs.com/en-US/External_Careers/job/Sr-Application-Engineer--f-m-d-_R51515__;!!IKRxdwAv5BmarQ!fQT9-IhPrQEiaF-bRh8kzm7ZUYiupEAP8lk9hFjLH8gH9DutbG6d_Im9CNd-75rBdJnCUB9XMbwEgEx6AQ$\">Sr. Application Engineer (f/m/d), Munich - Germany\u003C/a>\u003C/li>\u003C/ol>","2025-10-28T09:19:43.567Z","2025-10-29T07:09:08.732Z","2025-10-28T09:19:58.006Z","198",{"id":1165,"name":1166,"alternativeText":13,"caption":13,"width":1167,"height":1168,"formats":1585,"hash":1186,"ext":22,"mime":25,"size":1187,"url":1188,"previewUrl":13,"provider":54,"provider_metadata":13,"createdAt":1189,"updatedAt":1189},{"small":1586,"medium":1587,"thumbnail":1588},{"ext":22,"url":1171,"hash":1172,"mime":25,"name":1173,"path":13,"size":1174,"width":35,"height":584},{"ext":22,"url":1176,"hash":1177,"mime":25,"name":1178,"path":13,"size":1179,"width":42,"height":1180},{"ext":22,"url":1182,"hash":1183,"mime":25,"name":1184,"path":13,"size":1185,"width":105,"height":143},{"id":1385,"variation":58,"button":1590},[1591],{"id":404,"label":116,"size":62,"color":63,"style":13,"icon":117,"iconPosition":65,"url":1193,"newWindow":8,"downloadable":13,"shape":13},"-149",{"pagination":1594},{"page":5,"pageSize":373,"pageCount":69,"total":320},{"id":490,"heading":555,"pageHeader":1596,"sections":1598},{"id":490,"description":1597,"showPageHeader":8,"backgroundColor":81,"image":13},"CADathlon 2025 will be held as an in-person event",[1599,1609],{"id":535,"__component":1600,"componentVariation":1601,"styles":13,"header":13,"body":1602},"content.content","Content Image Left",{"id":1038,"title":13,"body":1603,"containerWidth":13,"buttonGroup":1604,"media":13},"\u003Ch4 class=\"h4\" style=\"margin-left:0px;text-align:justify;\">\u003Cspan style=\"color:rgb(83,127,154);\">\u003Cstrong>Sunday | October 26, 2025 | 8:00 - 17:00\u003C/strong>\u003C/span>\u003C/h4>\u003Cp style=\"margin-left:0px;text-align:justify;\">In-person | The Westin Grand Munich, Germany\u003C/p>\u003Cp style=\"margin-left:0px;text-align:justify;\">\u003Cspan style=\"background-color:rgb(255,255,255);color:rgb(34,34,34);\">The CADathlon is a challenging, all-day programming competition focusing on practical problems at the forefront of Computer-Aided Design and Electronic Design Automation in particular. The contest emphasizes the knowledge of algorithmic techniques for CADapplications, problem-solving and programming skills, and teamwork.\u003C/span>\u003Cbr>\u003Cbr>\u003Cspan style=\"background-color:rgb(255,255,255);color:rgb(34,34,34);\">As the “Olympic games of EDA,” the contest brings together the best and the brightest of the next generation of CAD professionals. It gives academia and the industry a unique perspective on challenging problems and rising stars, and it also helps attract top graduate students to the EDA field.\u003C/span>\u003Cbr>\u003Cbr>\u003Cspan style=\"background-color:rgb(255,255,255);color:rgb(34,34,34);\">The contest is open to two-person teams of undergraduate/graduate students specializing in CAD and currently full-time enrolled in a Ph.D. granting institution in any country. Students are selected based on their academic backgrounds and their relevant EDA programming experiences. Partial or full travel grants are provided to qualifying students (through ICCAD Student Scholar Program Grant). CADathlon competition consists of six problems in the following areas:\u003C/span>\u003Cbr>\u003Cbr>\u003Cspan style=\"background-color:rgb(255,255,255);color:rgb(34,34,34);\">Circuit Design & Analysis\u003C/span>\u003Cbr>\u003Cspan style=\"background-color:rgb(255,255,255);color:rgb(34,34,34);\">Physical Design & Design for Manufacturability\u003C/span>\u003Cbr>\u003Cspan style=\"background-color:rgb(255,255,255);color:rgb(34,34,34);\">Logic & High-Level Synthesis\u003C/span>\u003Cbr>\u003Cspan style=\"background-color:rgb(255,255,255);color:rgb(34,34,34);\">System Design & Analysis\u003C/span>\u003Cbr>\u003Cspan style=\"background-color:rgb(255,255,255);color:rgb(34,34,34);\">Functional Verification & Testing\u003C/span>\u003Cbr>\u003Cspan style=\"background-color:rgb(255,255,255);color:rgb(34,34,34);\">Future technologies (Bio-EDA, Security, AI, etc.)\u003C/span>\u003Cbr>\u003Cbr>\u003Cspan style=\"background-color:rgb(255,255,255);color:rgb(34,34,34);\">More specific information about the problems and relevant research papers will be released online one week before the competition. The writers and judges who construct and review the problems are experts in EDA from both academia and industry. Students will be given the problem statements and example test data at the contest, but they will not have the judges’ test data. Solutions will be judged on correctness and efficiency. Where appropriate, partial credit might be given.\u003C/span>\u003Cbr>\u003Cbr>\u003Cspan style=\"background-color:rgb(255,255,255);color:rgb(34,34,34);\">The team that earns the highest score is declared the winner. In addition to handsome trophies, the first-place and the second-place teams receive cash awards, and the contest winners will be announced at the ICCAD conference.\u003C/span>\u003C/p>\u003Chr>\u003Cp style=\"margin-left:0px;\">\u003Cstrong>Cash Prize\u003C/strong>\u003C/p>\u003Cul>\u003Cli>First Place Award: $1500 per person\u003C/li>\u003Cli>Second Place Award: $750 per person\u003C/li>\u003C/ul>\u003Chr>\u003Cp style=\"margin-left:0px;\">\u003Cspan style=\"background-color:rgb(255,255,255);color:rgb(34,34,34);\">\u003Cstrong>Participation Request\u003C/strong>\u003C/span>\u003Cbr>\u003Cspan style=\"background-color:rgb(255,255,255);color:rgb(34,34,34);\">Please submit your participation application via Google Form \u003C/span>by October 8th, 2025\u003C/p>\u003Chr>\u003Cp style=\"margin-left:0px;\">\u003Cstrong>2025 Organization Committee\u003C/strong>\u003C/p>\u003Cp>Nan Wu, George Washington University, USA\u003C/p>\u003Cp>Billy Pei-Yu Lee, Mediatek, TW\u003C/p>\u003Cp>Zahra Ghodsi, Purdue University, USA\u003C/p>\u003Cp>Amir Nassereldine, University at Buffalo\u003C/p>\u003Chr>\u003Cp>\u003Cspan style=\"background-color:transparent;color:#000000;\">\u003Cstrong>Problem contributors\u003C/strong>\u003C/span>\u003C/p>\u003Cp>\u003Cspan style=\"background-color:transparent;color:#000000;\">\u003Cstrong>Problem 1: \u003C/strong>\u003C/span>\u003Cspan style=\"background-color:#ffffff;color:#000000;\">\u003Cstrong>Passivity Enforcement for S-Parameter Modeling with Neural Networks\u003C/strong>\u003C/span>\u003C/p>\u003Cp>\u003Cspan style=\"background-color:transparent;color:#000000;\">\u003Cstrong>Topic chair: Zhou Jin (Zhejiang University)\u003C/strong>\u003C/span>\u003C/p>\u003Cp>\u003Cspan style=\"background-color:transparent;color:#000000;\">\u003Cstrong>Reference:\u003C/strong>\u003C/span>\u003C/p>\u003Cp>\u003Cspan style=\"background-color:transparent;color:#000000;\">Zeng, J. Sun, X. Wu, D. Niu, T. Wang, Y. Lin, Z. Ye, and Z. Jin, \"G-SpNN: GPU-Accelerated Passivity Enforcement for S-Parameter Modeling with Neural Networks,\" in 2025 62nd ACM/IEEE Design Automation Conference (DAC), pp. 1-6, 2025.\u003C/span>\u003C/p>\u003Cp>\u003Cspan style=\"background-color:transparent;color:#000000;\">\u003Cstrong>Problem 2: Sparse routing graph generation for fast initial global routing \u003C/strong>\u003C/span>\u003C/p>\u003Cp>\u003Cspan style=\"background-color:transparent;color:#000000;\">\u003Cstrong>Topic chair: William Chow (Cadence)\u003C/strong>\u003C/span>\u003C/p>\u003Cp>\u003Cspan style=\"background-color:transparent;color:#000000;\">\u003Cstrong>Reference:\u003C/strong>\u003C/span>\u003C/p>\u003Cp>\u003Cspan style=\"background-color:transparent;color:#000000;\">C. J. Alpert, T. C. Hu, J. H. Huang, A. B. Kahng and D. Karger, “Prim-Dijkstra Tradeoffs for Improved Performance-driven Routing Tree Design”, IEEE TCAD 14(7) (1995), pp. 890-896.\u003C/span>\u003C/p>\u003Cp>\u003Cspan style=\"background-color:transparent;color:#000000;\">\u003Cstrong>Problem 3: Timing-And-Power-Aware Multi-Bit Register Clustering\u003C/strong>\u003C/span>\u003C/p>\u003Cp>\u003Cspan style=\"background-color:transparent;color:#000000;\">\u003Cstrong>Topic chair: Wei-Che Tseng, Ting-Wei Lee, Jhih-Wei Hsu, Sheng-Wei Yang, Chin-Fang Cindy Shen (Synopsys Taiwan OPTO Physical Multibit & Hold team)\u003C/strong>\u003C/span>\u003C/p>\u003Cp>\u003Cspan style=\"background-color:transparent;color:#000000;\">\u003Cstrong>Reference:\u003C/strong>\u003C/span>\u003C/p>\u003Cp>\u003Cspan style=\"background-color:transparent;color:#222222;\">Yichen Cai, Linyu Zhu, and Xinfei Guo. 2025. Revisit MBFF: Efficient Early-Stage Multi-bit Flip-Flops Clustering with Physical and Timing Awareness. In Proceedings of the 30th Asia and South Pacific Design Automation Conference (ASPDAC '25).\u003C/span>\u003C/p>\u003Cp>\u003Cspan style=\"background-color:transparent;color:#222222;\">Cheng-Yen Li, Chuan-Chi Su, Zheng-Wei Chen, Shao-Hsiang Chen, and Yao-Wen Chang. 2025. Late Breaking Results: Multi-Objective Multi-Bit Flip-Flop Placement Considering Pre-Placed Cells. In Proceedings of the 62nd Annual Design Automation Conference (DAC '25)\u003C/span>\u003C/p>\u003Cp>\u003Cspan style=\"background-color:transparent;color:#222222;\">Ya-Chu Chang, Tung-Wei Lin, Iris Hui-Ru Jiang, and Gi-Joon Nam. 2019. Graceful Register Clustering by Effective Mean Shift Algorithm for Power and Timing Balancing. In Proceedings of the 2019 International Symposium on Physical Design (ISPD '19).\u003C/span>\u003C/p>\u003Cp>\u003Cspan style=\"background-color:transparent;color:#222222;\">Meng-Yun Liu, Yu-Cheng Lai, Wai-Kei Mak, and Ting-Chi Wang. 2022. Generation of Mixed-Driving Multi-Bit Flip-Flops for Power Optimization. In Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design (ICCAD '22).\u003C/span>\u003C/p>\u003Cp>\u003Cspan style=\"background-color:transparent;color:#222222;\">Gang Wu, Yue Xu, Dean Wu, Manoj Ragupathy, Yu-yen Mo, and Chris Chu. 2016. Flip-flop clustering by weighted K-means algorithm. In Proceedings of the 53rd Annual Design Automation Conference (DAC '16). \u003C/span>\u003C/p>\u003Cp>\u003Cspan style=\"background-color:transparent;color:#000000;\">\u003Cstrong>Problem 4: Broadcast Electrode-Addressing for EWOD Chips\u003C/strong>\u003C/span>\u003C/p>\u003Cp>\u003Cspan style=\"background-color:transparent;color:#000000;\">\u003Cstrong>Topic chair: Tsung-Wei Huang (University of Wisconsin at Madison)\u003C/strong>\u003C/span>\u003C/p>\u003Cp>\u003Cspan style=\"background-color:transparent;color:#000000;\">\u003Cstrong>Reference:\u003C/strong>\u003C/span>\u003C/p>\u003Cp>\u003Cspan style=\"background-color:transparent;color:#000000;\">\u003Cstrong>​​T. Xu and K. Chakrabarty, ''Broadcast electrode-addressing for pin-constrained multi-functional digital microfluidic biochips,'' Proc. ACM/IEEE Design Automation Conference, pp. 173-178, 2008.\u003C/strong>\u003C/span>\u003C/p>\u003Cp>\u003Cspan style=\"background-color:transparent;color:#000000;\">S. Kirpatrick, C. D. Gelatt, and M. P. Vecchi, \"Optimization by simulated annealing,\" Science, 200 (4598), pp. 671-680, 1983.\u003C/span>\u003C/p>\u003Cp>\u003Cspan style=\"background-color:transparent;color:#000000;\">\u003Cstrong>Problem 5: Efficient Symbolic Reasoning with Graph Learning\u003C/strong>\u003C/span>\u003C/p>\u003Cp>\u003Cspan style=\"background-color:transparent;color:#000000;\">\u003Cstrong>Topic chair: Nan Wu (George Washington University), Yingjie Li (Simon Fraser University)\u003C/strong>\u003C/span>\u003C/p>\u003Cp>\u003Cspan style=\"background-color:transparent;color:#000000;\">\u003Cstrong>Reference:\u003C/strong>\u003C/span>\u003C/p>\u003Cp>\u003Cspan style=\"background-color:transparent;color:#000000;\">Nan Wu, Yingjie Li, Cong Hao, Steve Dai, Cunxi Yu, and Yuan Xie. \"Gamora: Graph learning based symbolic reasoning for large-scale boolean networks.\" In Proceedings of the 60th ACM/IEEE Design Automation Conference (DAC), pp. 1-6. IEEE, 2023.\u003C/span>\u003C/p>\u003Cp>\u003Cspan style=\"background-color:transparent;color:#000000;\">\u003Cstrong>Problem 6: Quantum Circuit Synthesis\u003C/strong>\u003C/span>\u003C/p>\u003Cp>\u003Cspan style=\"background-color:transparent;color:#000000;\">\u003Cstrong>Topic chair: Zhiding Liang, Zhemin Zhang (Hong Kong University of Science and Technology)\u003C/strong>\u003C/span>\u003C/p>\u003Cp>\u003Cspan style=\"background-color:transparent;color:#000000;\">\u003Cstrong>Reference:\u003C/strong>\u003C/span>\u003C/p>\u003Cp>\u003Cspan style=\"background-color:transparent;color:#000000;\">J. Cheng, Y. Zhu, Y. Zhou, H. Ren, Z. Song, and Z. Liang, “EPOC: A Novel Pulse Generation Framework Incorporating Advanced Synthesis Techniques for Quantum Circuits,” May 06, 2024, arXiv: arXiv:2405.03804. doi: 10.48550/arXiv.2405.03804.\u003C/span>\u003C/p>\u003Chr>\u003Cp>\u003Cspan style=\"background-color:transparent;color:#000000;\">Previous CADathlon events: \u003C/span>\u003C/p>\u003Cul>\u003Cli>\u003Ca target=\"_blank\" rel=\"noopener noreferrer\" href=\"https://www.sigda.org/sigda-events/cadathlon/\">\u003Cspan style=\"background-color:transparent;color:#000000;\">https://www.sigda.org/sigda-events/cadathlon/\u003C/span>\u003C/a>\u003C/li>\u003Cli>\u003Cspan style=\"background-color:transparent;color:#000000;\">https://www.sigda.org/uncategorized/cadathlon-2022-problem-references/\u003C/span>\u003C/li>\u003C/ul>",{"id":647,"variation":58,"button":1605},[1606],{"id":609,"label":1607,"size":62,"color":63,"style":1608,"icon":117,"iconPosition":65,"url":13,"newWindow":8,"downloadable":13,"shape":13},"Sign Up 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