Sunday | October 26, 2025 | 8:00 - 17:00
In-person | The Westin Grand Munich, Germany
The CADathlon is a challenging, all-day programming competition focusing on practical problems at the forefront of Computer-Aided Design and Electronic Design Automation in particular. The contest emphasizes the knowledge of algorithmic techniques for CADapplications, problem-solving and programming skills, and teamwork.
As the “Olympic games of EDA,” the contest brings together the best and the brightest of the next generation of CAD professionals. It gives academia and the industry a unique perspective on challenging problems and rising stars, and it also helps attract top graduate students to the EDA field.
The contest is open to two-person teams of undergraduate/graduate students specializing in CAD and currently full-time enrolled in a Ph.D. granting institution in any country. Students are selected based on their academic backgrounds and their relevant EDA programming experiences. Partial or full travel grants are provided to qualifying students (through ICCAD Student Scholar Program Grant). CADathlon competition consists of six problems in the following areas:
Circuit Design & Analysis
Physical Design & Design for Manufacturability
Logic & High-Level Synthesis
System Design & Analysis
Functional Verification & Testing
Future technologies (Bio-EDA, Security, AI, etc.)
More specific information about the problems and relevant research papers will be released online one week before the competition. The writers and judges who construct and review the problems are experts in EDA from both academia and industry. Students will be given the problem statements and example test data at the contest, but they will not have the judges’ test data. Solutions will be judged on correctness and efficiency. Where appropriate, partial credit might be given.
The team that earns the highest score is declared the winner. In addition to handsome trophies, the first-place and the second-place teams receive cash awards, and the contest winners will be announced at the ICCAD conference.
Cash Prize
- First Place Award: $1500 per person
- Second Place Award: $750 per person
Participation Request
Please submit your participation application via Google Form by October 8th, 2025
2025 Organization Committee
Nan Wu, George Washington University, USA
Billy Pei-Yu Lee, Mediatek, TW
Zahra Ghodsi, Purdue University, USA
Amir Nassereldine, University at Buffalo
Problem contributors
Problem 1: Passivity Enforcement for S-Parameter Modeling with Neural Networks
Topic chair: Zhou Jin (Zhejiang University)
Reference:
Zeng, J. Sun, X. Wu, D. Niu, T. Wang, Y. Lin, Z. Ye, and Z. Jin, "G-SpNN: GPU-Accelerated Passivity Enforcement for S-Parameter Modeling with Neural Networks," in 2025 62nd ACM/IEEE Design Automation Conference (DAC), pp. 1-6, 2025.
Problem 2: Sparse routing graph generation for fast initial global routing
Topic chair: William Chow (Cadence)
Reference:
C. J. Alpert, T. C. Hu, J. H. Huang, A. B. Kahng and D. Karger, “Prim-Dijkstra Tradeoffs for Improved Performance-driven Routing Tree Design”, IEEE TCAD 14(7) (1995), pp. 890-896.
Problem 3: Timing-And-Power-Aware Multi-Bit Register Clustering
Topic chair: Wei-Che Tseng, Ting-Wei Lee, Jhih-Wei Hsu, Sheng-Wei Yang, Chin-Fang Cindy Shen (Synopsys Taiwan OPTO Physical Multibit & Hold team)
Reference:
Yichen Cai, Linyu Zhu, and Xinfei Guo. 2025. Revisit MBFF: Efficient Early-Stage Multi-bit Flip-Flops Clustering with Physical and Timing Awareness. In Proceedings of the 30th Asia and South Pacific Design Automation Conference (ASPDAC '25).
Cheng-Yen Li, Chuan-Chi Su, Zheng-Wei Chen, Shao-Hsiang Chen, and Yao-Wen Chang. 2025. Late Breaking Results: Multi-Objective Multi-Bit Flip-Flop Placement Considering Pre-Placed Cells. In Proceedings of the 62nd Annual Design Automation Conference (DAC '25)
Ya-Chu Chang, Tung-Wei Lin, Iris Hui-Ru Jiang, and Gi-Joon Nam. 2019. Graceful Register Clustering by Effective Mean Shift Algorithm for Power and Timing Balancing. In Proceedings of the 2019 International Symposium on Physical Design (ISPD '19).
Meng-Yun Liu, Yu-Cheng Lai, Wai-Kei Mak, and Ting-Chi Wang. 2022. Generation of Mixed-Driving Multi-Bit Flip-Flops for Power Optimization. In Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design (ICCAD '22).
Gang Wu, Yue Xu, Dean Wu, Manoj Ragupathy, Yu-yen Mo, and Chris Chu. 2016. Flip-flop clustering by weighted K-means algorithm. In Proceedings of the 53rd Annual Design Automation Conference (DAC '16).
Problem 4: Broadcast Electrode-Addressing for EWOD Chips
Topic chair: Tsung-Wei Huang (University of Wisconsin at Madison)
Reference:
T. Xu and K. Chakrabarty, ''Broadcast electrode-addressing for pin-constrained multi-functional digital microfluidic biochips,'' Proc. ACM/IEEE Design Automation Conference, pp. 173-178, 2008.
S. Kirpatrick, C. D. Gelatt, and M. P. Vecchi, "Optimization by simulated annealing," Science, 200 (4598), pp. 671-680, 1983.
Problem 5: Efficient Symbolic Reasoning with Graph Learning
Topic chair: Nan Wu (George Washington University), Yingjie Li (Simon Fraser University)
Reference:
Nan Wu, Yingjie Li, Cong Hao, Steve Dai, Cunxi Yu, and Yuan Xie. "Gamora: Graph learning based symbolic reasoning for large-scale boolean networks." In Proceedings of the 60th ACM/IEEE Design Automation Conference (DAC), pp. 1-6. IEEE, 2023.
Problem 6: Quantum Circuit Synthesis
Topic chair: Zhiding Liang, Zhemin Zhang (Hong Kong University of Science and Technology)
Reference:
J. Cheng, Y. Zhu, Y. Zhou, H. Ren, Z. Song, and Z. Liang, “EPOC: A Novel Pulse Generation Framework Incorporating Advanced Synthesis Techniques for Quantum Circuits,” May 06, 2024, arXiv: arXiv:2405.03804. doi: 10.48550/arXiv.2405.03804.
Previous CADathlon events:
- https://www.sigda.org/sigda-events/cadathlon/
- https://www.sigda.org/uncategorized/cadathlon-2022-problem-references/