Silence of the Chips: Advanced Techniques in Hardware Vulnerability Detection
Monday | October 27, 2025 | 10:00 - 11:30
The ever-increasing complexity of microprocessors has resulted in several potent security threats in recent years. These vulnerabilities in the hardware arising from unchecked performance optimizations have been exploited through various ways, such as micro-architectural attacks, fault injections, memory corruption, and other forms of information leakage. Post tape-out, hardware vulnerabilities are typically mitigated using software updates or hardware recall, which result in unacceptably high performance or economic overheads, respectively. Thus, there is a pressing need to uncover these vulnerabilities during the hardware design phase. Integrating such approaches can improve the overall security, reliability, and economic viability of microprocessors. In this tutorial, we introduce hardware vulnerabilities and state-of-the-art techniques to uncover these vulnerabilities at design time, leveraging hardware fuzzing, AI, and formal verification. Tutorial participants will gain an understanding of the fundamentals of hardware vulnerabilities, their origins, and detection approaches. We will present some of the potent Common Weakness Enumerations (CWEs) we have exposed in popular microprocessors. With our assistance, participants will get a real-world demonstration of the hardware fuzzing techniques used to detect these vulnerabilities and pinpoint their location in hardware design. We will explore the recent advances in hardware fuzzing using AI techniques and formal verification. We will use concrete, hands-on examples to quantitatively analyze the potential of these techniques for hardware security and the open challenges in the domain.